SPICE Model
PDK
Standard Cell
Chip-to-Package Connectivity Verification Solution
Verifies integrated system connection with extraction of connectivity between chip and package design
Completes I/O pad configuration planning and chip-to-package connectivity verification with package design in an early stage to shorten product launch cycle
Seamless and robust chip-to-package connectivity verification
Error-free chip-to-package connectivity engagement
Easy and convenient error-debugging environment
User-oriented chip-to-package specification
Fast debugging TAT to reduce long design iteration
Support various package types
Efficient communication method
Package design interface
Back-end design
with RDL
IO Pad & Bump
configuration planning
